Globalfoundries validated 28nm AMS production and revealed digital and AMS support for double patterning at the 20nm node:
At next week’s Design Automation Conference (DAC) in San Francisco, Calif., GLOBALFOUNDRIES plans to demonstrate an enhanced silicon-validated design flow for its 28nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG). The flow provides proven and complete front-to-back support for advanced analog/mixed-signal (AMS) design using the industry’s latest design automation technology. In addition, the company will reveal jointly developed design flows with its EDA partners in certifying both analog and digital “double patterning aware” flows for its 20nm process, with silicon validation expected in early 2013 at that technology node.
As a result of GLOBALFOUNDRIES’ commitment to silicon validation of flows before releasing them, customers have the confidence to produce signoff-ready 28nm digital and analog designs using the industry's most advanced set of design tools, tool scripts, and methodologies from the leading EDA suppliers. The company’s tight collaboration with the design tool and IP ecosystem also accelerates its ability to develop working flows for advanced nodes such as 20nm, providing their advantages in gate density, performance, and lower power to customers ahead of other foundries.
“Our approach to early collaborative development work with our design enablement partners continues to keep us at the leading-edge of process technology and deliver proven and reliable solutions to customers,” said Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES. “At 28nm, and even more so at 20nm, process technology and design tool flows must be in lock step in order to address the significant design-to-manufacturing challenges that arise. We work closely with our partners to identify innovative approaches to deal with challenges such as timing variations for digital ICs and layout dependent effects in custom chips. These most recent flows demonstrate the strength of our model, as well as the innovation and expertise required to offer foundry solutions at this level.”
Enhanced flow support at 28nm
The GLOBALFOUNDRIES 28nm AMS production flow is a Mixed Vendor Flow supporting tools from multiple vendors, including Cadence Design Systems for layout with Virtuoso technology; Synopsys and Cadence for parasitic extraction; and Mentor Graphics for physical verification. The flow is a truly integrated mixed-signal flow with complete support for a digital implementation module based on the Encounter Digital Implementation System from Cadence. This proven approach enables the integration of analog IP into a digital SOC design using production standard cells.
In addition, the flow now includes inductor synthesis and extraction support from specialized EDA suppliers Lorentz Solutions, Helic and Integrand Software. The flow has also been augmented with support for fast variation-aware analysis using the Variation Designer platform from Solido Design Automation, and EM/IR analysis using the Totem software platform from Apache Design. A DRC waiver flow is available from Mentor Graphics’ Calibre tool suite.
The 28nm AMS Production Design flow is fully validated with silicon results from an analog design with validated functionality from 300MHZ up to 3Ghz. Silicon validation included clock duty cycle, peak-to-peak period jitter and operating current for key analog blocks.
The 28nm flow leverages GLOBALFOUNDRIES' heritage as a leader in Design-for-Manufacturing (DFM) by supporting DRC+, the company's silicon-validated solution that goes beyond standard Design Rule Checking (DRC) and uses two-dimensional shape-based pattern-matching to enable up to a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy.
As part of the design flow support, customers receive the entire design database, detailed documentation and executable flow scripts, and also a report on the testing results of the manufactured silicon. The flows are fully integrated with the PDK and maintained and supported by GLOBALFOUNDRIES.
Enabling double patterning at 20nm
At 20nm, GLOBALFOUNDRIES and its design enablement partners have focused on critical new manufacturability issues, including the limits of traditional lithography and the need for even more robust DFM techniques. A key requirement is double patterning "the splitting of metal layers into two masks" a technique that is best supported in customers’ design flows.
GLOBALFOUNDRIES has developed two fully executable 20nm RTL2GDSII flows for its 20nm process, one based on the Galaxy suite of tools from Synopsys and the other based on the Cadence Encounter platform. Both flows are being silicon validated by designing a complex double patterned test chip. The flows support synthesis, color aware place-and-route, parasitic extraction, STA and physical verification. Mentor Graphics Calibre is used for decomposition and physical verification. The flows support the use of double patterning at each step of the design process, including ‘double patterning aware’ placement, routing, optimization, extraction, and physical verification. The double pattering support also allows the customer to choose to decompose portions of the different mask themselves or to use an automated approach for decomposing the masks and assigning colors.