When the embedded DRAM scales down, the capacitance of the deep trench capacitor decreases. To compensate for the decreased capacitance, the R&D team introduced a bottle etching process combined with a structure named LOCOS collar, which allows forming the trench in a bottle like shape. The trench, therefore, is wide but has a narrow month that increases the trench's surface area, increasing capacitance.The companies have jointly developed 90nm and 65nm process technologies and are now in the third phase of the 45nm process development. More details about the development can be found at EET
Sony and Toshiba's embedded DRAM goes 45nm
Posted on Saturday, June 18 2005 @ 5:21 CEST by Thomas De Maesschalck
Sony and Toshiba have developed the first 45nm embedded DRAM cell by scaling embedded DRAM cells down to 0.069 square microns.