Applied Materials announced the development of a new manufacturing technique that it claims will enable chipmakers to build interconnects far smaller than the current 20nm limit. The firm claims its new technology will be able to achieve 10nm or less, full details at Bit Tech.
Although it's not obvious to look at them, a modern semiconductor can contain more than 60 linear miles of copper wiring across as many as 10 billion vertical connections. As process sizes shrink and increasing features are added to chips, that figure is only going to rise - and that's a real problem.
Where the interconnects meet the chip features, the wiring needs to be the same size. The result: tiny copper wires just 20nm wide for the latest generation of NAND flash parts. Creating these interconnects at such a small size causes real problems, largely due to bubbles forming as the small holes are filled with copper to create the connection. Back when interconnects were larger, these small bubbles didn't cause too much of a problem - but below 20nm a single bubble in a single interconnect can render a chip useless, meaning yields drop through the floor.