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BIOS Option Of The Week - PCI Master Bus TimeOut Control at TechARP

Posted on Sunday, August 19 2012 @ 19:05:26 CEST by


This week TechARP discusses the PCI Master Bus TimeOut Control setting, you can read about it over here.
What this BIOS feature does is limit the time a device has to start writing data to the PCI bus. If the first data write by the device cannot be completed by the timeout period, then it is disconnected and control of the PCI bus granted to another device. This prevents a stalled device from unnecessarily tying up the PCI bus.

When set to any integer from 1 to 7, all PCI devices must abide by a timeout period for the first data transfer. The timeout period is calculated by multiplying the value set with 32 clock cycles. For example, if you set it to 2, then the timeout period will be 64 clock cycles.

When set to Disabled, this feature is disabled and PCI devices can take as long as they want to complete their first data transfer. Even if the device stalls, it will not release control of the PCI bus.

It is recommended that you set a short timeout period to prevent any stalled device from hogging the PCI bus.




 



 

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