Though several development programs are underway, including the G450C program, it is uncertain when all of the necessary tools will be in place to support 450-mm wafers. Wang reportedly said TSMC would complete specification setting for 450-mm tools in 2014 or 2015 and set up pilot lines in 2016 or 2017 prior to volume in 2018.Further details about TSMC's plans can be read at EE Times.
The Taiwan Economic News reported that Burn Lin, TSMC's vice president of R&D, speaking at the same press conference ahead of Semicon Taiwan, said that TSMC will begin volume production of FinFET transistors at the 20-nm process node and is on the track to deploy a full FinFET process at the 16-nm node. Lin reportedly added that TSMC will use immersion lithography for 16-nm and 10-nm production but that multi e-beam lithography is a candidate for a 10-nm FinFET process.
TSMC delays 450mm wafer plans to 2018
Posted on Wednesday, Sep 05 2012 @ 22:17 CEST by Thomas De Maesschalck