Intel expects to use at least double patterning in some layers of some chips at 14 nm. If immersion is used at 10 nm, more layers will require double patterning and some will even require quadruple patterning, he said.
At 14 nm, Bohr said, "the increased wafer costs [associated with double patterning] is still being offset by improved density, so our cost per transistor continues to go down with each generation on a very steady trend,” he said.
That trend would continue, he suggested, even if immersion is used at 10 nm. As of today, “EUV is later than I would like, and I can’t count on it for sure,” he said.
“We are probably the last company continuing to stay on a pace of having a new process technology every two years or so,” Bohr said in his talk.
Intel on track for 14nm chips before end of 2013
Posted on Thursday, September 13 2012 @ 14:39 CEST by Thomas De Maesschalck