Moore's Law sketches out the concept of shrinking semiconductor device dimensions, but the shrinking of technology nodes will have to overcome some challenges, particularly cost-related barriers. The transition to 20nm process technology shows that the pace of cost reduction for transistor production has been slowing, Sun pointed out.
Transition to a newer process should enable a 25% improvement in performance, and the manufacturing cost per transistor should also fall at the same rate in order to be cost effective, Sun said. The current shift to 20nm process from 28nm has encountered problems associated with rising equipment costs for double patterning techniques, and performance is only able to see a 15% improvement, Sun indicated.
"Based on our IBM FinFET licensing, UMC has decided to aggressively develop 14nm FinFET technology on 20nm metal. 14nm FinFET will deliver the most optimal low-power and high-performance solution to offset the cost impact from using double patterning lithography," Sun said.
UMC reveals 14nm FinFET process plans
Posted on Friday, November 02 2012 @ 16:03 CET by Thomas De Maesschalck