Building on the high-performance XDR memory interface technology, the XDR2 memory interface is targeting applications that require extreme memory bandwidth, such as 3D graphics, advanced video imaging, and network routing and switching applications. In order to achieve high bandwidth efficiency and data rates of 8GHz and beyond the XDR2 memory interface incorporates:
"We are continually pushing interface technology forward to develop compelling and innovative solutions that meet our customers' needs," said Laura Stark, vice president of the Platform Solutions Group at Rambus. "XDR2 is our latest iteration of the XDR DRAM architecture and will help 3D games and graphics-intensive applications realize the high performance potential that users demand."
Micro-threading -- a DRAM core innovation developed to increase memory system efficiency to enable DRAMs to provide more usable data bandwidth to requesting memory controllers, while minimizing power consumption; Adaptive Timing -- a speed enhancement to today's XDR FlexPhase timing circuits that compensates for process, voltage and temperature variations during real-time operation; Transmit Equalization -- an output circuit that minimizes the adverse system effects of reflections and attenuation that typically limit the speed of DRAM systems; DRSL Signaling -- a 200mV differential signaling standard that provides superior common mode noise rejection with an on-chip terminated point-to-point topology that minimizes reflections and reduced signal transition times associated with device loading and PCB trace stubs.
Rambus engineers work closely with chip and system companies to optimize the DRAM controllers to take advantage of the performance benefits that the XDR2 solution provides. The XDR2 memory interface is available for licensing now and could be shipping in products by 2007.