Bit Tech reports Intel and the Industrial Technology Research Institute of Taiwan (ITRI) have announced their progress on the development of a next-generation high-speed memory architecture that promises better performance and lower power consumption. Intel didn't reveal exact details, but Bit Tech speculates the ITRI memory array involves the use of a 2D grid-like array or even a 3D array to boost data density and increase inter-cell communication performance.
Intel and ITRI announced their partnership back in December 2011, working to improve both the performance and memory efficiency of dynamic memory (DRAM) as part of Intel's Ultrabook slim form-factor laptop project. The idea was to use ITRI's research know-how and Intel's access to fabrication facilities - and, let's not forget, near-limitless quantities of R&D cash - to develop next-generation memory architectures for mobile devices that would boost battery life considerably over current-generation parts.
A year on, and that partnership is beginning to bear fruit: Intel's chief technology officer Justin Rattner held a press conference in Taipei earlier this week to announce the development of an experimental memory architecture. Sadly, Intel isn't quite ready to share the details, beyond the focus on interconnect technologies between memory cells and the use of an array-like structure.