Posted on Saturday, December 08 2012 @ 16:27 CET by Thomas De Maesschalck
This week TechARP discusses the DRAM Burst Length 8QW BIOS setting, you can learn about it
over here.
This BIOS feature allows you to control the length of a burst transaction.
When this feature is set to Disabled, a burst transaction can only comprise of up to four quadword (QW) reads or writes.
When this feature is set to Enabled, a burst transaction can only comprise of up to eight quadword (QW) reads or writes.
As the initial CAS latency is fixed for each burst transaction, a longer burst transaction will allow more data to be read or written for less delay than a shorter burst transaction. Therefore, a burst length of 8 will be faster than a burst length of 4.
Therefore, it is recommended that you enable this BIOS feature for better performance.
