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Rambus reveals the R+ LPDDR3 memory architecture

Posted on Tuesday, January 29 2013 @ 12:20:32 CET by

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Rambus announced the R+ LPDDR3 memory standard, a new architecture that promises higher frequencies and lower power consumption than traditional LPDDR3. The standard is fully compatible with DFI and JEDEC industry standards and is a low-sing implementation of the Rambus near ground signaling technology that enables higher data rates with significantly reduced IO power, while remaining fully backward compatible with LPDDR3.
“The R+ LPDDR3 technology enables the mobile market to use our controller and DRAM solutions to provide unprecedented levels of performance, with a significant power savings,” said Kevin Donnelly, senior vice president and general manager of the memory and interface division at Rambus.

The R+ LPDDR3 architecture includes both a controller and a DRAM interface and can reduce active memory system power by up to 25% and supports data rates of up to 3200MHz, which is double the performance of existing LPDDR3 technologies. These improvements to power efficiency and performance enable longer battery life and enhanced mobile device functionality for streaming HD video, gaming and data-intensive apps. The R+ LPDDR3 is also available with Rambus’ collaborative design and integration services. Rambus provides silicon-proven design of R+ LPDDR3 memory controller in Globalfoundries’ 28nm-SLP process technology. It is unclear which memory makers will product R+ LPDDR3 chips.
Source: X-bit Labs



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