Intel already has a 22-nm chip fabrication process that uses a "3D" gate structure, but that's not what Esfarjani is talking about. 3D NAND refers to flash memory that stacks multiple cell layers on top of each other. EE Times notes that Toshiba has been hyping 3D NAND tech for years, and that it's due to start sampling a 16-layer device this year. Esfarjani told the conference that 32-64 layers are needed to make 3D flash cost-effective.
3D NAND is probably a few years away, so what's IMFT working on for the 2D stuff? Nitride film and nanodots, according to Esfarjani. It's unclear whether either will be necessary to shrink cells for 15-nm production, but the challenge appears to be making the cells last with that smaller geometry. As NAND cells shrink, their write/erase endurance tends to degrade.
IMFT: 2D flash to scale down to 10nm
Posted on Wednesday, May 29 2013 @ 20:00 CEST by Thomas De MaesschalckIM Flash Technologies, the flash joint venture of Intel and Micron, anticipates traditional NAND flash memory will scale down to 10nm. CEO Keyvan Esfarjani said that 15nm and 10nm is possible with current NAND structures, and that 3D NAND structures should carry the technology beyond 10nm.
