Posted on Tuesday, October 22 2013 @ 11:39 CEST by Thomas De Maesschalck
X-bit Labs
writes some more details were revealed about AMD's next-generation Excavator chip. This fourth-generation Bulldozer will offer 256-bit AVX2 floating point instruction support, and will support all other instructions found in Intel's Haswell processor. Excavator is currently slated for 2015 or even 2016, by that time Intel is expected to release Skylake, a new architecture that will support 512-bit AVX 3.2 instructions.
The original AVX brought 256-bit floating-point SIMD instructions, the AVX2 allows to operate with the AVX 256-bit wide YMM register for integer data types. The problem with current AMD hardware is that the Bulldozer FPU only supports 128-bit integer operations used in the XOP instruction set, reports HardwareLuxx web-site.
To support AVX2 instructions, AMD will need to either considerably upgrade its FPU [floating point unit], which is shared between two ALUs in a Bulldozer module, or even develop a new one from scratch. The new one will expectedly feature dramatic performance improvements, but even a redesigned one should be noticeably faster than existing one in numerous demanding applications that process loads of data.
