Intel and TSMC want to use the ultra-fine patterning systems to make their generation of 7 and 10 nanometer chips starting in about 2017. But such aspirations have been dashed many times: EUV was originally targeted at use as early as 2007. Making chips is "becoming a game of accounting for every nanometer, and that's not possible without a rigorous and mathematically sound approach," said Mark C. Phillips, head lithography engineer for Intel, in an interview with EE Times.
At the SPIE Lithography conference here, Phillips disclosed a new analysis tool under development at ASML for handling edge placement errors in next-generation chips, a growing problem with multiple causes. Just one aspect of the new modeling tool "takes about 10 pages of math to explain," said Phillips who asked ASML to start working on the concept after a meeting last year.
Intel and TSMC talk up EUV efforts
Posted on Thursday, February 27 2014 @ 10:34 CET by Thomas De MaesschalckEE Times reports both Intel and TSMC revealed new efforts towards extreme ultraviolet lithography, a technique that promises to make it easier to make smaller, faster chips in the future.
