AMD Carrizo APU to use stacked DRAM?

Posted on Monday, Jul 14 2014 @ 10:55 CEST by Thomas De Maesschalck
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Italian tech site Bits and Chips heard rumors that AMD plans to use stacked DRAM memory on its Carrizo APU.

This will be a solution primarily for the high-end APU and APU dedicated server markets, it promises to minimize the latency and overhead between the CPU and GPU and will be more cost-effective than on-die L3 cache.

The site claims the stacked memory will achieve higher speeds and lower latencies than DDR4, without the high cost of DDR4 memory. The die size of Carrizo will reportedly be smaller than Kaveri, the APU itself will be made on a 28nm process while the stacked DRAM will be fabbed on 20nm.


About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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