The difference between first-gen and second-gen HBM is pretty big, the second-gen doubles the bandwidth and enables higher memory density. The exact tweaks required to support HBM2 are unknown, it could be a simple PCB revision or a more complicated GPU revision.
4-HI HBM1 has a 1024-bit interface, can handle two prefetch operations per IO and has a maximum bandwidth of 128GB per second. The tRC is 48nm, with tCCD of 2ns (1tCK), and the VDD voltage of 1.2V. For example GDDR5 has 1.35 to 1.5V and a top bandwidth of 28GB/s throughput per chip.
The 4-Hi HBM2 solution, according official SK Hynix data provided to Fudzilla, has 1024 bit I/O, two prefects operations per IO, and 64 Byte access granularity (=I/O x prefetch). The maximum possible bandwidth with HBM 2 doubles to 256GB per chip at the same 48nm tRC, with tCCD of 2ns (1tCK), and the VDD voltage of 1.2V.