More details about AMD's future x86 Zen APU have been uncovered by FUD Zilla! These APUs will feature up to 16 cores and will support 32 threads, each core reportedly has 512KB L2 cache and each cluster of four Zen cores gets a shared 8MB L3 cache.
This means the 16-core versions come with 8MB L2 and 32MB L3 cache. One of the new things in the Zen series will be the inclusion of integrated graphics with HBM memory, the architecture reportedly supports up to 16GB of HBM memory with 512GB/s of bandwidth. We presume this is primarily for the HPC server versions, the consumer versions are unlikely to end up with so much memory.
Other than that, Zen also adds DDR4 support and has 64 PCIe 3.0 lanes:
The next generation Zen based APU also comes with PCIe Gen3 support and SATA express or SATA, 1GbE support and DDR4 memory controllers in 4x72 configuration. The 4-channel DDR4 supports ECC memory and speeds up to 3200 MHz, SODIMM, UDIMM, RDIMM, LRDIMM 2DIMMs/channel, with total capacity of 256GB per channel. That is a lot of memory.
The APU has 64 PCI express Gen 3 lanes, where 16 lanes are switchable with 2 lanes or SATA Express and 14 lanes of SATA. AMD is using coherent fabrics to interconnect the Zen CPU die and Greenland graphics die, and it also uses coherent fabric for inter communication between Zen die CPUs and Caches, PSP, Times, counters, ACPI or Legacy interface, GMI Physics, Combo Physics, Host Controllers like USD, SATA or GbE and Memory controllers. GMI stands for Global Memory interconnect and this is the interface between Zen die and Greenland die, or between two chips on the same multi-chip module package.