Samsung adds 10nm FinFET to its foundry roadmap

“We have a full PDK [process development kit] and silicon-verified IP available, and are, currently, running MPWs [multi-project wafer] now for our lead customers,” said Kelvin Low, senior director of marketing at Samsung Foundry. “With mass production scheduled from late 2016 we are excited about this next phase of our foundry business. Early designs activities have already sparked some interesting discussions.”

Samsung’s 10nm fabrication process is an all-new technology that features its own back-end-of-line interconnect flow in addition to all new front-end-of-line features, providing performance, power and area scaling. It is expected that Samsung’s 10nm FinFET sports considerably smaller transistor fin, transistor gate and interconnect pitches compared to the company’s 14nm process technologies. Shrinking geometry of all pitches results in higher performance, increased transistor density and lower per-transistor costs, something that will be a huge benefit for many companies who use Samsung Foundry’s services.