The Taiwanese foundry also made a working prototype of a 10nm FinFET chip. The 10nm FinFET node promises 0.52x area scaling versus 20nm and either 18 percent higher speed or 40 percent less power consumption than TSMC's 16FF+ process. The downside though is that 10nm requires triple patterning and an entire new EDA (electronic design automation) design flow. Full details at EE Times.
The road map suggests TSMC could leapfrog Intel to producing 10nm chips, although naming conventions for nodes these days hide the underlying details of the processes. What's more clear is TSMC has gotten off to a slow start with its 16nm FinFET process with close partners such as Xilinx saying they have taped out but not yet shipped their first chip in the process. Xilinx also plans to skip TSMC’s 10mn process in favor of its 7nm node, a significant choice given Xilinx typically acts as a logic driver for new TSMC nodes.