JEDEC updates LPDDR3 and LPDDR4 standards

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD209-4A, Low Power Double Data Rate 4 (LPDDR4) and JESD209-3C Low Power Double Data Rate 3 SDRAM (LPDDR3). The updates are designed to enhance performance capabilities for these mobile memory standards, which significantly boost memory speed and efficiency for mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, both updates are available for free download from the JEDEC website.

When first published in August 2014, LPDDR4 represented a dramatic performance increase over the prior version of the standard. In order to achieve even higher performance, the latest revision adds skew definitions between dies on the channel (rank to rank parameters such as tDQS2DQ_rank2rank and tDQSCK_rank2rank). These definitions address DRAM process variation and allow the SoC to better manage DRAM timing with less complexity. JESD209-4A also adds new eMCP (embedded multi-chip packages) and provides key errata missing from the original standard.

First published in May 2012, JESD209-3 LPDDR3 was designed to offer a higher data rate, improved bandwidth and power efficiency, and higher memory densities over its groundbreaking predecessor, LPDDR2. Still widely used in array of mobile products, this latest update to LPDDR3 offers new package configurations:

136-ball PoP (eMMC + LPDDR3)

272-ball dual-Channel POP

221-ball single channel MCP

In addition, lower DRAM densities addressing has been added and a “refresh multiplier” parameter (tREFIM = RM x tREFI) was also introduced.

“JEDEC remains committed to developing standards that meet the performance demands required by the latest mobile products, and that effort includes updating our existing standards to serve the industry’s needs,” said Mian Quddus, JEDEC Board of Directors Chairman.