There's not a lot of news to go around today, guess we're starting to enter the quiet period before the holiday season so news updates on DV Hardware will probably become a bit less frequent.
One snippet I do have for you is that TSMC has started work on its 5nm process mode. TSMC CEO Mark Liu detailed the foundry's future plans at a recent supply chain management conference at the company's HQ in Hsinchu, Taiwan. Hexus writes TSMC is currently in the process of technology qualification for the 10nm process, with the first customer tapeouts planned for early 2016. The foundry made its first functional 7nm SRAM chip in October 2015 and believes it can kick off volume production in 2017.
Not a lot of information was revealed about the 5nm node though. Work on this manufacturing process is in the early stages, and TSMC is yet to decide whether to adopt extreme ultraviolet litograpy (EUV) at the 5nm node.
EE Times writes a combination of 193-immersion and EUV may be the best solution for the 5nm node, given the immature state of EUV:
A 193i-only approach is potentially the most expensive, requiring quad patterning for metal layers and triple patterning for vias. An all-EUV approach needs fewer layers and supported better area, power and performance but it is not practical given the still immature state of EUV systems.
The extension of 193nm immersion to 7nm and beyond is possible, yet it would require octuple patterning and other steps that would increase production costs. It could become a speed bump for chipmakers planning to adopt finer geometries, slowing the growth of the chip industry.