Micron may have 768Gb TLC NAND flash memory chips in its pipeline

Posted on Monday, Feb 08 2016 @ 15:09 CET by Thomas De Maesschalck
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Micron presented a next-generation 768Gbit triple-bit-per-cell (TLC) NAND flash memory design at last week's International Solid-State Circuits Conference (ISSCC). The 768Gb 3D NAND device from Micron has a density of 4.29Gb/mm2 compared to 2.6Gb/mm2 for the most dense 256Gbit 3D NAND chips that Samsung ships today, and four times as much as most planar devices available on the market today.

The company has not yet decided whether it will commit to manufacturing the design as a product. The product would have a chip die size of 179.2mm², read speeds of up to 800MB/s and write speed of 44MB/s. This compares to a die size of 97.6mm² for the Samsung device, which has a read speed of 178MB/s but a write speed of 53MB/s.
Given the four-to-one ratio of Micron’s density compared to today’s planar devices, the company can afford to spend a lot on the new product and still make a profit, Harari said. However, he noted it may require the equivalent of a new fab.

The Micron part gets its density from a technique of tucking control circuitry under the array pioneered years ago by Matrix Semiconductor and used by several companies including SanDisk, he added.

“Micron is bold in designing this chip whether they can yield it is another matter,” Harari said.
Toshiba/SanDisk plan on offering 768Gb TLC 3D BiCS by late 2017 and promise to offer 1Tbit chips in 2018.

Micron TLC goes 768Gb

Source: EE Times


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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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