The chip is based on Toshiba's media embedded processors (MePs) and features nine instruction execution pipelines and a re-order buffer circuit to manage and shorter waiting cycles for user extension instructions.
The core is based on a 32 bit RISC chip and produced on a 65nm process, but it's also possible to create it at 90nm. The MeP-h1 is aimed at the digital TV and DVD market.
Source: The Inq