Samsung mass produces its first 10nm FinFET SoCs

Samsung announced it kicked off mass production of its first SoCs made on a 10nm FinFET (10LPE) process. The South Korean firm says the first smartphones with 10nm chips are expected to hit retail shelves in early 2017.

Compared with Samsung's 14nm process, the 10nm chips promise up to 30 percent increase in area efficiency, with 27 percent higher performance or 40 percent lower power consumption. A more efficient 10LPP process is expected to be ready late next year. As a reminder, these 10nm nodes from Samsung are for mobile chips only, they won't be used for more powerful applications like GPUs.

Intel is expected to roll out its first 10nm chips in 2017, TSMC aims at a similar timeframe but indicated its 10nm process will be short-lived and GlobalFoundries is skipping 10nm altogether in favor of going straight to 7nm. Also keep in mind that these days the numeral before "nanometer" is little more than marketing. For example, the general idea seems to be that these "10nm" nodes are just catching up with Intel's "14nm" process and that the latter's "10nm" will be quite a bit ahead.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it has commenced mass production of System-on-Chip (SoC) products with 10-nanometer (nm) FinFET technology for which would make it first in the industry.

Following the successful mass production of the industry’s first FinFET mobile application processor (AP) in January, 2015, Samsung extends its leadership in delivering leading-edge process technology to the mass market with the latest offering.

“The industry’s first mass production of 10nm FinFET technology demonstrates our leadership in advanced process technology,” said Jong Shik Yoon, Executive Vice President, Head of Foundry Business at Samsung Electronics. “We will continue our efforts to innovate scaling technologies and provide differentiated total solutions to our customers.”

Samsung’s new 10nm FinFET process (10LPE) adopts an advanced 3D transistor structure with additional enhancements in both process technology and design enablement compared to its 14nm predecessor, allowing up to 30-percent increase in area efficiency with 27-percent higher performance or 40-percent lower power consumption. In order to overcome scaling limitations, cutting edge techniques such as triple-patterning to allow bi-directional routing are also used to retain design and routing flexibility from prior nodes.

Following the introduction of Samsung’s first-generation 10nm process (10LPE), its second generation process (10LPP) with performance boost is targeted for mass production in the second half of 2017. The company plans to continue its leadership with a variety of derivative processes to meet the needs of a wide range of applications.

Through close collaboration with customers and partners, Samsung also aims to cultivate a robust 10nm foundry ecosystem that includes reference flow verification, IPs and libraries.

Production level process design kits (PDK) and IP design kits are currently available for design starts.

SoCs with 10nm process technology will be used in digital devices launching early next year and are expected to become more widely available throughout 2017.