TSMC to use EUV for enhanced version of its 7nm process, 12nm is not for high-end GPUs

Posted on Friday, Mar 17 2017 @ 15:25 CET by Thomas De Maesschalck
TSMC logo
More details about TSMC's future process technologies were revealed at the TSMC Symposium Santa Clara 2017. The company said it will adopt extreme ultraviolet (EUV) lithography for an enhanced version of its 7nm FinFET node, announced a 22nm planar rival for GlobalFoundries' upcoming 22nm FD-SOI and revealed more about its 12nm process.

TSMC revealed it's getting 76 percent yields on 256Mbit SRAM made on its first-generation 7nm node. This process is expected to enter volume production next year and ARM is reportedly achieving frequencies in excess of 4GHz for its Cortex-A72 using a new design flow. Risk production of 7nm chips is expected to start next month, with the first of 12 tapeouts planned in May.

The enhanced 7+ process, which will be the first TSMC process to adopt EUV, will reportedly offer 1.2x greater logic density and 10 percent more speed or 15 percent higher energy efficiency versus the foundry's first-generation 7nm node. TSMC is confident it can achieve volume production of 7+ in 2019:
The foundry achieved similar yields using immersion and EUV steppers on a 7nm test chip. In addition, it hit 125W with its ASML 3350 EUV system, providing confidence it can hit about 250W for high volume manufacturing with EUV in 2019 on a 7+nm process.
Volume production of 10nm is a priority this year, this process is primarily for Apple's mobile chips and will be short-lived. TSMC also shared it plans to get 5nm in volume production in 2020 and that its R&D lab is working on enabling nodes at and beyond 3nm:
Meanwhile in its R&D labs, TSMC has built next-generation transistors out of horizontally stack gate-all-around nanowires. It has also demonstrated the structures using germanium. The company also mentioned work in new interconnects and a back-end capping process, all aimed at enabling nodes at and beyond 3nm.
Last but not least, some information was provided about 12nm. TSMC plans a six-track 12nm FinFET process but it appears this will not be for high-end GPUs. This contradicts some of the rumors we heard about NVIDIA going 12nm for its high-end Volta GPU. Instead, 12nm will be for mid-range mobile and video processors, as well as high-end IoT applications. High-end GPUs use 16FF+ and are expected to migrate to 10/7nm.
The 16FFC process which has had eight design wins is not yet in volume production. The 12FFC process should start risk production before June and deliver 1.1x the speed or 0.7x the power of 16FFC process.

Compared to 16FFC, 12nm chips running at less than 2.4 GHz could see 20 percent area shrinks. Those running faster than 2.4 GHz could be optimized for an additional six percent in speed gains.
A four-page report about the event can be read at EE Times.

About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

Loading Comments