Intel Skylake-X and server chips adopt mesh bus architecture

Intel's upcoming Skylake-SP server chips as well as the Skylake-X for the high-end desktop market will use a new bus architecture. Since the Nehalem days, Intel used a ring-bus architecture but now the company is switching to a mesh architecture, which promises to be more scalable and modular. The new architecture is more suitable for many-core designs and delivers a lot more bandwidth, while also lowering power consumption.

Intel explains how it all works on its blog.

The Intel® Xeon® Scalable processors implement an innovative “mesh” on-chip interconnect topology that delivers low latency and high bandwidth among cores, memory, and I/O controllers. Figure 1 shows a representation of the mesh architecture where cores, on-chip cache banks, memory controllers, and I/O controllers are organized in rows and columns, with wires and switches connecting them at each intersection to allow for turns. By providing a more direct path than the prior ring architectures and many more pathways to eliminate bottlenecks, the mesh can operate at a lower frequency and voltage and can still deliver very high bandwidth and low latency. This results in improved performance and greater energy efficiency similar to a well-designed highway system that lets traffic flow at the optimal speed without congestion.