First up is the announcement from WD, they say they're planning to sample the 96-layer 3D NAND in the second half of this year with initial production expected in 2018. The 96-layer NAND will be used for TLC and QLC NAND memory chips. Initial models will feature 256Gb (32GB) on a single chip, like the prototype sample the company is showing today, while later models will feature up to 1Tb (125GB).
Western Digital Corp. (NASDAQ: WDC), a global data storage technology and solutions leader, today announced that it has successfully developed its next-generation 3D NAND technology, BiCS4, with 96 layers of vertical storage capability. Sampling to OEM customers is expected to commence in the second half of calendar year 2017 and initial production output is expected in calendar year 2018. BiCS4, which was developed jointly with Western Digital's technology and manufacturing partner Toshiba Corporation, will be initially deployed in a 256-gigabit chip and will subsequently ship in a range of capacities, including a terabit on a single chip.Toshiba's announcement also says they'll be offering 96-layer 32GB flash memory chips in 2018. The upcoming 96-layer chips cut costs by allowing a capacity increase of about 40 percent versus 64-layer models.
"Our successful development of the industry's first 96-layer 3D NAND technology demonstrates Western Digital's continued leadership in NAND flash and solid execution to our technology roadmap," said Dr. Siva Sivaram, executive vice president of memory technology at Western Digital. "BiCS4 will be available in 3-bits-per-cell and 4-bits-per-cell architectures, and it contains technology and manufacturing innovations to provide the highest 3D NAND storage capacity, performance and reliability at an attractive cost for our customers. Western Digital's 3D NAND portfolio is designed to address the full range of end markets spanning consumer, mobile, computing and data center."
The company also highlighted strong ongoing operations at its joint venture manufacturing facilities in Japan. In particular, the company reiterated its expectation that in calendar year 2017, the output mix of its 64-layer 3D NAND technology, BiCS3, will comprise more than 75 percent of its overall 3D NAND bit supply. The company now believes that, along with its partner Toshiba Corporation, the combined 64-layer 3D NAND bit output of the joint ventures in calendar year 2017 will be higher than any other industry supplier in calendar year 2017.
Toshiba Memory Corporation, the world leader in memory solutions, today announced that it has developed a prototype sample of 96-layer BiCS FLASH™ three-dimensional (3D) flash memory with a stacked structure, with 3-bit-per-cell (triple-level cell, TLC) technology. Samples of the new 96-layer product, which is a 256 gigabit (32 gigabytes) device, are scheduled for release in the second half of 2017 and mass production is targeted for 2018. The new device meets market demands and performance specifications for applications that include enterprise and consumer SSD, smartphones, tablets and memory cards.
Going forward, Toshiba Memory Corporation will apply its new 96-layer process technology to larger capacity products, such as 512 gigabit (64 gigabytes) and 4-bit-per-cell (quadruple-level cell, QLC) technology, in the near future.
The innovative 96-layer stacking process combines with advanced circuit and manufacturing process technology to achieve a capacity increase of approximately 40% per unit chip size over the 64-layer stacking process. It reduces the cost per bit, and increases the manufacturability of memory capacity per silicon wafer.
Since announcing the world’s first prototype 3D flash memory technology in 2007, Toshiba Memory Corporation has continued to advance development of 3D flash memory and is actively promoting BiCS FLASH™ to meet demand for larger capacities with smaller die sizes.
This 96-layer BiCS FLASH™ will be manufactured at Yokkaichi Operations in Fab 5, the new Fab 2, and Fab 6, which will open in summer 2018.