Posted on Monday, July 24 2017 @ 12:02 CEST by Thomas De Maesschalck
EE Times
had an interview with AMD CTO Mark Papermaster about process technology and chip stacks. As you may know, AMD's second-generation and third-generation Zen designs will be made on the 7nm process. Papermaster explains 7nm will be a long node, similar to the 28nm process, and reveals it's "the toughest lift he's seen in a number of generations."
To gear up for 7nm, “we had to literally double our efforts across foundry and design teams…It’s the toughest lift I’ve seen in a number of generations,” perhaps back to the introduction of copper interconnects, said Mark Papermaster, in a wide-ranging interview with EE Times.
The 7nm node requires new “CAD tools and [changes in] the way you architect the device [and] how you connect transistors—the implementation and tools change [as well as] the IT support you need to get through it,” he said.
Papermaster predicts foundries will start using extreme ultraviolet (EUV) lithography in 2019 and he urges them to go as fast as they can. The interview also deals with chip stacking, a technology he sees as key for "an era of Moore's law-plus."
