Posted on Wednesday, October 18 2017 @ 10:46 CEST by Thomas De MaesschalckEE Times offers some coverage of what we can expect from both companies, as well as the other speakers at the event:
Intel will discuss several aspects of its 10nm node first unveiled in March. It sports FinFETs with a 7nm fin width at a 34nm pitch and a 46nm fin height made using self-aligned quadruple patterning. A 204 Mbit SRAM made in the process packs separate high-density, low voltage and high-performance cells that measure from 0.0312µm2 to 0.0441µm2.
The 12-metal interconnect layers in the node can support multiple threshold voltages. Compared to its 14nm process, the 10nm node sports NMOS and PMOS current that is 71 percent and 35 percent greater. Cobalt wires in the lowest two metal layers offer up to 10x improvement in electro-migration and a 2x reduction in via resistance.
