PCI Express 4.0 final spec is ready

PCI-SIG announced the completion of version 1.0 of the PCI Express 4.0 specification. Not a lot of surprises here, this standard doubles the bandwidth to 16GT/s and offers some other enhancements like reduced system latency, lane margining, higher scalability, and improved I/O virtualization and platform integration.

The delivery of the PCIe 4.0 specification to the industry is an important addition to our spec library as it delivers high performance 16GT/s data rates with flexible lane width configurations, while continuing to meet the industry’s requirements for low power.

Additional functional enhancements include:

Extended tags and credits for service devices

Reduced system latency

Lane margining

Superior RAS capabilities

Scalability for added lanes and bandwidth

Improved I/O virtualization and platform integration

And we’ve seen unprecedented early adoption! Prior to publication, we’ve had numerous vendors confirmed with 16GT/s PHYs in silicon and IP vendors already offering 16GT/s controller. Given the interest, we held a pre-publication Compliance Workshop with preliminary FYI Testing Only for PCIe 4.0 architecture that attracted dozens of solutions. We’re continuing to conduct FYI testing in our workshops throughout the remainder of the year.

It took a long time for PCI Express 4.0 to be ready but future revisions will come a lot faster as the enterprise world is really craving a lot more bandwidth. PCI-SIG recently released PCI Express 5.0 version 0.3 and expects the final version of that specification will be ready in Q2 2019. PCI Express 5.0 will double the bandwidth once more to 32GT/s.

While there are no consumer motherboards yet with PCI Express 4.0 support, the upcoming Intel Optane SSD 900p will be one of the first consumer-oriented storage devices with support for the new standard.