Posted on Sunday, March 25 2018 @ 18:57 CEST by Thomas De Maesschalck
At a Synopsys user group event in Santa Clara, EE Times
picked up musings that the path to 2nm chips may not be worth it. Engineers see a viable path to scale down silicon transistors to 5nm, 3nm, and even 2nm nodes, but some are doubting whether there will be sufficient commercial advantages. It's still too early to know for sure, but the increasing complexity and higher costs of ever-smaller chips may mean that even 5nm is too small to make economic sense:
Speed gains of 16% at 10 nm may dry up at 7 nm due to resistance in metal lines. Power savings will shrink from 30% at 10 nm to 10–25% at 7 nm, and area shrinks may decline from 37% at 10 nm to 20–30% at 7 nm, said Paul Penzes, a senior director of engineering on Qualcomm’s design technology team.
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“Area still scales in strong double digits, but the hidden cost increases in masks means the actual cost advantages and other improvements are starting to slow down … It’s not clear what will remain at 5 nm,” said Penzes, suggesting that 5-nm nodes may only be extensions of 7 nm.
