Blayne Curtis - Barclays Capital, Inc.
Hey, thanks for taking the question. I just want to ask you about 7-nanometer. You mentioned TAM and timing there, and I don't expect you to put a date out there for 7-nanometer. So maybe you can talk about what you've learned on 10-nanometer, how you're applying it to 7-nanometer, and any indications of that development, how it's going.
Venkata S. M. Renduchintala - Intel Corp.
Sure. Blayne, so 7-nanometer is very much R&D in deep progress, and we're making good progress on that development. We're not giving a direct timeline right now. But we've also made some fairly judicious choices in defining 7-nanometer, learning from our 10-nanometer experiences. And we're focusing on an optimum balance point between density, power and performance, and schedule predictability. So I think what you'll see is a more balanced approach across those three vectors.
So we're still going to drive density but balancing that with a continued focus on driving transistor performance at the same time, which is highly valued as ASP drivers both in our client and server businesses. And we're really also focusing on being much more precise in our ability to launch. So those are the key learnings that are coming out of 10-nanometer as we go into 7-nanometer. And as we monitor progress on 7-nanometer just as closely as we are on 10-nanometer, I feel those lessons are being well absorbed into our progress, and we're lining up to support our product plans as our roadmap dictates.
Intel: Lessons learned from 10nm applied on 7nm
Posted on Friday, Jul 27 2018 @ 09:38 CEST by Thomas De Maesschalck