Posted on Thursday, November 01 2018 @ 11:10 CET by Thomas De Maesschalck
Phoronix
discovered hints about new Zen 2 instructions in a GNU Compiler Collection (GCC) 9 patch from AMD. In particular, this patch reveals new CPU instructions like Cache Line Write Back (CLWB), Read Processor ID (RDPID), and Write Back and Do Not Invalidate Cache (WBNOINVD). Not really major stuff, but it could be that there's more that AMD doesn't want to reveal at this time.
That's it in terms of new instructions, at least what's enabled by these patches. It's possible there might be some other new instructions supported by Zen 2 that AMD doesn't want to reveal at this time, just like the scheduler cost tables haven't yet been tuned, etc. This patch is basically a starting point so the GCC 9.1 stable update due out in 2019 can at least handle -march=znver2 and that march=native targeting will also work for these next-gen AMD processors.
The first chips based on the Zen 2 architecture are the 7nm EPYC 2 processors, which are expected by early 2019. After that, there will be a Ryzen 3000 series.
