AMD EPYC Rome may feature double the L3 cache

Posted on Monday, Nov 26 2018 @ 11:24 CET by Thomas De Maesschalck
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A new SiSoft Sandra database entry offers some clues about the cache configuration of AMD's upcoming 7nm EPYC "Rome" server processor. Based on the Zen 2 design, this server chip will pack up to eight 7nm eight-core CPU chiplets in combination with a central 14nm I/O controller die.

If the read-out from SiSoft Sandra is accurate, it looks like the Rome chips have 512KB L2 cache per core and 16x 16MB L3 cache. The L3 cache is double as much as the first-gen EPYC processors:
For each 64-core "Rome" processor, there are a total of 8 chiplets. With SANDRA detecting "16 x 16 MB L3" for 64-core "Rome," it becomes highly likely that each of the 8-core chiplets features two 16 MB L3 cache slices, and that its 8 cores are split into two quad-core CCX units with 16 MB L3 cache, each. This doubling in L3 cache per CCX could help the processors cushion data transfers between the chiplet and the I/O die better. This becomes particularly important since the I/O die controls memory with its monolithic 8-channel DDR4 memory controller.
Via: TPU

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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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