Industry-First 3D Stacking of Logic Chips: Intel demonstrated a new 3D packaging technology, called "Foveros," which for the first time brings the benefits of 3D stacking to enable logic-on-logic integration.
Foveros paves the way for devices and systems combining high-performance, high-density and low-power silicon process technologies. Foveros is expected to extend die stacking beyond traditional passive interposers and stacked memory to high-performance logic, such as CPU, graphics and AI processors for the first time.
The technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in new device form factors. It will allow products to be broken up into smaller "chiplets," where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top.
Intel expects to launch a range of products using Foveros beginning in the second half of 2019. The first Foveros product will combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die. It will enable the combination of world-class performance and power efficiency in a small form factor.
Foveros is the next leap forward following Intel's breakthrough Embedded Multi-die Interconnect Bridge (EMIB) 2D packaging technology, introduced in 2018.
Intel Foveros enables logic-on-logic 3D stacking
Posted on Wednesday, December 12 2018 @ 15:39 CET by Thomas De Maesschalck