Dongkyun Kim, a Hynix chip designer, presented the ISSCC paper Wednesday on the Hynix DDR5 chip, a 16Gb 6.4Gb/s/pin SDRAM that runs at 1.1V and measures 76.22mm2. The device is fabricated in a 1ynm, 4-metal DRAM process.
Kim described the implementation of a modified delay-locked loop (DLL) using a phase rotator and an injection locked oscillator to reduce clock jitter and clock duty cycle distortion associated with operating at higher clock speeds. He also described other techniques used by the Hynix design team, including a write-level training method to offset clock-domain issues associated with higher speeds and a modified forward feedback equalization (FFE) circuit.
SK Hynix detailed its DDR5 tech at ISSCC
Posted on Friday, February 22 2019 @ 11:09 CET by Thomas De Maesschalck