Intel bfloat16 instruction set exclusively for Cooper Lake Xeon Scalable?

Posted on Monday, Apr 08 2019 @ 15:08 CEST by Thomas De Maesschalck
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AnandTech reports a new version of Intel's software developer documentation reveals the Xeon Scalable "Cooper Lake-SP" processors will introduce support for AVX512_BF16 instructions and therefore the bfloat16 format. Oddly enough, the documentation seems to suggest the bfloat16 instructions will only be supported by Cooper Lake-SP, and not Ice Lake-SP, the chip's direct successor.
The bfloat16 is a truncated 16-bit version of the 32-bit IEEE 754 single-precision floating-point format that preserves 8 exponent bits, but reduces precision of the significand from 24-bits to 8 bits to save up memory, bandwidth, and processing resources, while still retaining the same range. The bfloat16 format was designed primarily for machine learning and near-sensor computing applications, where precision is needed near to 0 but not so much at the maximum range. The number representation is supported by Intel’s upcoming FPGAs as well as Nervana neural network processors, and Google’s TPUs. Given the fact that Intel supports the bfloat16 format across two of its product lines, it makes sense to support it elsewhere as well, which is what the company is going to do by adding its AVX512_BF16 instructions support to its upcoming Xeon Scalable ‘Cooper Lake-SP’ platform.
The site reached out to Intel and received word that the chip giant does not provide guidance beyond Cooper Lake.


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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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