How Intel foresees a 50x increase in logic density

Yesterday we already wrote about the Jim Keller talk about the future of Moore's Law and how Intel is working on "significantly bigger" CPU architectures. One of the things the CPU architect revealed is that Intel sees a path to 50x logic scaling from the current 10nm node.

Tom's Hardware writer witeken zooms in on how Intel plans to achieve this:

Fin pitch can scale from 34 to 24nm with 2 fins/x'tor (3x) (7nm?). Nanowire (5nm?) will allow stacking the wires (2x) and stacking P/NMOS (2x). Going vertically on chip scale could yield another 4x.

Despite the massive difficulties with 10nm, it seems Intel is still optimistic about future opportunities.

A proposed path by Jim Keller to 50x logic density scaling from 10nm.

Fin pitch can scale from 34 to 24nm with 2 fins/x'tor (3x) (7nm?). Nanowire (5nm?) will allow stacking the wires (2x) and stacking P/NMOS (2x). Going vertically on chip scale could yield another 4x. pic.twitter.com/IPgAldThsL

— witeken (@witeken) September 22, 2019