TSMC and ARM show off new 7nm 3DIC chiplet system

Posted on Monday, Sep 30 2019 @ 09:24 CEST by Thomas De Maesschalck
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Last week at TSMC’s Open Innovation Platform Ecosystem Forum in Santa Clara, the Taiwanese foundry and CPU architecture designer ARM showed off a new 7nm chiplet system. The proof-of-concept featured various ARM cores and TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) packaging to deliver a high-performance, 7nm FinFET chip capable of running at 4GHz.

Similar to Intel's Foveros packaging technology, the technique enables each chiplet to be made on a different process node. The idea here is that by using multiple small chiplets, instead of a big monolithic core, you can achieve better yields and cheaper chips.
Rather than the typical SoC with system components arranged on a single die, a chiplet system is optimized for modern HPC processors that partition large multi-core designs into smaller chipsets. This approach allows each chiplet — each die in a package of multiple dice — to be built in different process technologies. The approach is expected to deliver better yields and overall cost-effectiveness.
Full details EE Times.


About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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