Similar to Intel's Foveros packaging technology, the technique enables each chiplet to be made on a different process node. The idea here is that by using multiple small chiplets, instead of a big monolithic core, you can achieve better yields and cheaper chips.
Rather than the typical SoC with system components arranged on a single die, a chiplet system is optimized for modern HPC processors that partition large multi-core designs into smaller chipsets. This approach allows each chiplet — each die in a package of multiple dice — to be built in different process technologies. The approach is expected to deliver better yields and overall cost-effectiveness.Full details EE Times.