Early 5nm chips from TSMC achieving 80 percent yields

Last week, TSMC talked about the yields of its 5nm test chips at the IEEE IEDM Conference. This new process offers a full node increase versus 7nm, it features fifth generation FinFET and uses EUV over 10+ layer. The N5 process shares some design rules with TSMC's 7nm nodes so clients should be able to migrate a bit more easily.

Early 5nm SRAM test chips are currently achieving average yield rates of 80 percent. This is for very small chips of course, the current yields for larger chips are a lot lower. AnandTech calculated that a 100mm² chip would currently have a yield of about 32 percent, which is actually pretty good considering the 5nm process is still in the middle of risk production. TSMC expects to offer 5nm volume production in the first half of 2020.

If you’re only here to read the key numbers, then here they are. In the disclosure, TSMC is stating that their 5nm EUV process affords an overall with a ~1.84x logic density increase, a 15% power gain, or a 30% power reduction. The current test chip, with 256 Mb of SRAM and some logic, is yielding 80% on average and 90%+ in peak, although scaled back to the size of a modern mobile chip, the yield is a lot lower. The technology is currently in risk production, with high volume production scheduled for the first half of 2020. This means that chips built on 5nm should be ready in the latter half of 2020.