Western Digital and Kioxia (formerly Toshiba Memory) are now manufacturing 112-layer BiCS5 3D NAND flash memory. At the moment, the companies are producing 512Gbit TLC chips in limited volume. Higher volume is expected in the second half of the year. The companies are also planning 112-layer 1Tbit TLC as well as 1.33Tbit QLC chips.
The BiCS5 design uses 112 layers compared to 96 for BiCS4. BiCS5 is the second generation from WDC/Kioxia to be constructed with string stacking, and is probably built as two stacks of about 56 active layers each. Even though 112 layers is only a ~16% increase over the previous generation, the companies are claiming a density increase of up to 40% (comparing 112L 512Gb TLC against 96L 256Gb TLC, by bits per wafer), thanks to other tweaks to the design that allow for shrinking horizontal dimensions. The density of the memory array itself is said to be about 20% higher. The memory interface speed has been increased by 50%, which should put it at 1.2GT/s, on par with most of the 96L competitors.
The first SSDs based on 112-layer BiCS5 are expected towards the end of the year. The transition to this new type will be slower than before.