Posted on Monday, April 20 2020 @ 12:29 CEST by Thomas De Maesschalck
TSMC revealed that the design target for its 3nm process is to be able to pack 250 million transistors per square millimeter. TechPowerUp
points out that this basically means something the size of a pin head will be able to pack the same number of transistors as an Intel Pentium 4 processor die.
Experts are of the opinion that sub-5 nm nodes will require major innovations with materials and structures. TSMC claims that N3 will provide a 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed, compared to N5.
The N3 node from TSMC is expected to be ready for mass production in the second half of 2022. Risk production will start sometime next year.
