The idea here is that such a hybrid chip can deliver high-performance when needed, while running more energy efficient when possible. Tom's Hardware notes that on the surface, it appears the technique AMD is describing requires less operating system intervention as it seems to allow the processor to independently figure out which type of thread should run on each cluster:
The method described in AMD's patent appears to allow the processor to independently sort out which type of thread should run on each cluster based on the instructions supported by the cores within. The threads could also shift between the cores based on utilization. For example, if the large core is underutilized, the processor would shift the thread to the small core (provided it supports the instructions). If the small core is over-utilized, the thread would shift to the larger core (again, provided it supports the instructions).As always, keep in mind that this is just a patent application. It means AMD is researching a possible own implementation of big.LITTLE but it doesn't necessarily mean it will actually make it into a future product. The patent is also still in the adjustment phase, so still subject to change
The approach appears to reduce or negate the need for OS intervention for some types of thread movements. The patent also explains an example wherein the clusters of cores could be CPUs, GPUs, or DSPs, meaning there's a dizzying array of possible combinations.
Patent: Instruction subset implementation for low power operation - AMD
— Underfox (@Underfox3) August 8, 2020
Basically, AMD BIG.little.
This patent still in the adjustment process.
More Details: https://t.co/7pPd3NSXj2 pic.twitter.com/pN5OiHi4BS