Ex-Intel engineer sheds light on why 10nm and 7nm is in tatters

Up until a couple of years ago, Intel was seen as the pinnacle of semiconductor engineering. The company's tick-tock model delivered a steady stream of enhancements but the multi-year delay of the 10nm node (and now also the 7nm issues) have tarnished Intel's reputation.

Now a former Chinese-language employee of Intel sheds some light on what went wrong at the chip giant's manufacturing arm. As always, take this with a grain of salt, but it's an interesting read nonetheless.

Twitter user Retired Engineer offers a translation over here and NotebookCheck has a summarized version over here. The engineer talks about the hostile work environment at Intel, the unrealistic expectations, high turnover rates, the bad cooperation between the CPU design and the manufacturing team, etc.

Here's a snipper from NotebookCheck that reveals what went wrong with 7nm:

About a year ago, Intel tried to plan for the 7 nm transition and placed Chia-Hong in charge. However, because of all the problems with the 10 nm process, Intel decided to relax things for the 7 nm node, even though the new process would require the use of the revolutionary gate-all-around (GAA)FET manufacturing process. Intel was warned by TSMC and Samsung that the GAA-FET technique is too challenging to implement at this point in time, but Intel’s pride and persistence led it to stubbornly try and tackle the GAA-FET problem, until it finally conceded this July. The initial 7 nm designs now need to be further simplified and Intel is trying to cut a deal with TSMC.