Basically, Intel's goal is to gradually move to computer chips that consist of many chiplets. At first, the goal is to switch from monolithic designs to chips from multiple dies, like what AMD is doing today. After that, the plan is to split everything into small chiplets. Basically, the CPU will consist of a collection of chiplets, the integrated graphics will be a bunch of chiplets and the I/O will also be composed of a number of chiplets.
Intel sees several benefits. Verification is done at the IP/chiplet level and there will be significant reuse potential. The chip giant promises this will cut development time of a chip to just one year (versus 3-4 years for monolithic chips) and reduce the number of bugs found in silicon to "under 10", down from "over 100s" in monolithic designs.
AnandTech offers some commentary over here. The site sees various advantages but points out that Intel hasn't spoken much about how "Client 2.0" is supposed to be glued together. Intel would need something like AMD's Infinity Fabric to pull this off.
The only downside here is that Intel hasn’t spoken much about the glue that binds it all together. Chiplet strategies rely on complex high-speed interconnect protocols, custom or otherwise. Current uses of Intel’s die-to-die connectivity are either simply memory protocols or FPGA fabric extensions – the big ones for server CPUs like UPI aren’t necessarily up to the task. CXL could be the future here, however current CXL is built upon PCIe, which means a complex CXL/PCIe controller for every chiplet which will likely get power hungry fast.