AMD CTO Mark Papermaster talks about Zen 3

Posted on Tuesday, Oct 20 2020 @ 13:06 CEST by Thomas De Maesschalck
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AnandTech scored an interview with AMD CTO Mark Papermaster about the Zen 3 architecture, you can read it over here. The first Zen 3-based Ryzen 5000 series processors will hit the market on November 5th. This new 7nm generation promises 19 percent higher instructions per clock (IPC) versus the previous generation, has a new core layout, a higher max boost, and a new cache topology. Performance-per-Watt is even better with a 24 percent increase!
IC: Speaking to that process node, TSMC’s 7nm as you said: we’ve specifically been told that it is this sort of minor process update that was used for Ryzen 3000XT. Are there any additional benefits that Ryzen 5000 is getting through the manufacturing process that perhaps we are not aware of?

MP: It is in fact the core is in the same 7nm node, meaning that the process design kit [the PDK] is the same. So if you look at the transistors, they have the same design guidelines from the fab. What happens of course in any semiconductor fabrication node is that they are able to make adjustments in the manufacturing process so that of course is what they’ve done, for yield improvements and such. For every quarter, the process variation is reduced over time. When you hear ‘minor variations’ of 7nm, that is what is being referred to.

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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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