Besides process technology, foundries like TSMC are also innovating with packaging technology.
TSMC has reportedly started testing its 6th generation Chip-on-Wafer-on-Substrate (CoWoS) packaging technology. According to media reports, the new technology enables the placement of 12 stacks of HBM on a single package. Mass production is expected in 2023.
The new generation is said to enable a massive 12 stacks of HBM memory on a package. You are reading that right. Imagine if each stack would be an HBM2E variant with 16 GB capacity that would be 192 GB of memory on the die present. Of course, that would be a very expensive chip to manufacture, however, it is just a showcase of what the technology could achieve.