AMD patents reveals GPU chiplet design details

Posted on Monday, Jan 04 2021 @ 10:38 CET by Thomas De Maesschalck
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It's no secret that future GPUs will likely feature a lot more chiplets rather than the current monolithic designs. This is something that AMD, Intel, and NVIDIA have been researching for some time now but it's still unknown when the results of this work will hit the market.

Just before the end of 2020, a patent application from AMD about GPU chiplets got published online. This application was filed in June 2019 a SoC with a CPU and a GPU chiplet array. The first GPU chiplet communicates to the CPU via a bus, whereas all other GPU chiplets communicate with the first GPU chiplet via a passive crosslink. Each chiplet features its own last-level cache that is "communicably coupled" to physical resources so the cache is "unified and coherent across all GPU chiplets."
AMD thinks that it would be possible to avoid such problems by implementing ‘high bandwidth passive crosslinks. According to AMD, the first GPU chipset would be direct ‘communicably coupled’ to the CPU, while each of the GPU chiplets in the array would be coupled to the first GPU via a passive crosslink. In this sense, AMD considered passive crosslink as communication wires between chiplets that are placed on a single interposer. (in multiple layers if needed). Such GPU group would work as a System on a Chip, which is divided into different functional chips.
More details at VideoCardz. It's rumored that RDNA3+ may be the first AMD GPU architecture to adopt the chiplet approach.



About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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