Details leak about NVIDIA GeForce RTX 3080 Ti and RTX 3070 Ti -- plus A100 for mining (updated)

Despite the chip shortages, more video card SKUs are still on the way. NVIDIA for example is said to be working on two new cards for the higher-end segment.

GeForce RTX 3080 Ti with GA102-225

According to VideoCardz, NVIDIA's add-in board (AIB) partners have finally receivedf the first embargoed information about the GeForce RTX 3080 Ti video card. Rumors about this model have been circulating around the web for many months. It now seems the April launch is getting more likely.

The GeForce RTX 3080 Ti uses the PG132 SKU 18 board design and features the GA102-225 GPU. It's unknown how this chip differs versus the previously rumored GA102-250. VideoCardz' sources do indicate the 12GB GDDR6X memory rumor is accurate.

NVIDIA's partners reportedly did not receive more detailed information about the GPU. If things go as planned, the GeForce RTX 3080 Ti will hit retail shelves by mid-April.

And GeForce RTX 3070 Ti with GA104-400

There are also some tidbits about the GeForce RTX 3070 Ti -- this will allegedly hit the market by the end of May. The GeForce RTX 3070 Ti gets the GA104-400 GPU, which is rumored to feature 6144 CUDA cores, and 8GB GDDR6X memory.

Both models are believed to feature the Ethereum hash-rate limiter, but given recent developments, this seems kinda pointless if NVIDIA doesn't make substantial changes.

NVIDIA GA100 GPU getting CMP HX mining launch?

kopite7kimi claims NVIDIA is working on a mining variant of the GA100 GPU. This is the flagship Ampere GPU -- at the moment it's exclusive available for the HPC market because it's geared towards compute workloads. The known Twitter leaker claims the A100 is a mining monster.

The A100 cards from NVIDIA cost around $10,000 but the green team could create cheaper mining variants. The A100 is equipped with 40GB HBM2, this could be cut to a single 8GB HBM2 stack for mining purposes.

The A100 Tensor Core offers up to 19.5 TLFOPs in single-precision calculations. The card is also equipped with high-speed (1.6 TB/s) 40GB HBM2 of memory. Both values are very important in mining. GA100-based mining solution probably wouldn’t need all five stacks of HBM2 memory, a single 8GB HBM2 stack would suffice. Current DAG (Directed Acyclic Graph) size 3.49 GB for Ehtereum and 3.58 GB for Ethereum Classic. A reduction to single stack HBM2 would have noticeably reduced the cost of such a solution.

Take it with a grain of salt, but according to Twitter leaker I_Leak_VN, this model could be launched as the NVIDIA CMP 220HX. With an estimated Ethereum mining performance of 210MH/s it would be an absolute beast. Pricing is said to be $3,000.

Synology preps first PCI Express 6.0 solutions

In related news, work on the first PCI Express 6.0 solutions is well underway. Towards the end of this year, we can expect the first consumer platform with PCI Express 5.0 support, via the arrival of Intel's Alder Lake-S and the 600-series chipset. Looking a bit further into the future, PCI Express 6.0 is expected to double the bandwidth versus PCI Express 5.0. The PCI Express 6.0 specification will be finalized later this year but Synology is already announcing the first complete IP solution:

Synopsys, Inc. (Nasdaq: SNPS) today announced the industry's first complete IP solution for the PCI Express® (PCIe®) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys' widely deployed and silicon-proven DesignWare® IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state. Synopsys' complete IP solution addresses evolving latency, bandwidth and power-efficiency requirements of high-performance computing, AI and storage SoCs.

To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design. The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

Synopsys' DesignWare PHY IP for PCIe 6.0 provides unique adaptive DSP algorithms that optimize analog and digital equalization to maximize power efficiency regardless of the channel. The PHY enables near zero link downtime using patent-pending diagnostic features. The placement-aware architecture of the DesignWare PHY IP for PCIe 6.0 minimizes package crosstalk and allows dense SoC integration for x16 links. The optimized datapath with ADC-based architecture achieves ultra-low latency.

I mean we will meet a new CMP HX card based on A100.

— kopite7kimi (@kopite7kimi) March 21, 2021