AMD patent reveals chiplet GPU with active bridge

Posted on Monday, Apr 05 2021 @ 16:34 CEST by Thomas De Maesschalck
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A new AMD patent sheds some light on the company's chiplet development. The patent was filed on September 27, 2019 and got published late last week. It describes an active bridge chiplet with integrated Infinify Cache memory.

It's been rumored for some time now that future GPU designs from AMD will feature a chiplet-based approach instead of one big monolithic die. A previous AMD patent that covered chiplet technology featured a passive bridge design and the new patent describes an upgraded version with an active inter-chiplet bridge that would feature an integrated L3 cache.
AMD explains that any inter-chiplet communication would be routed through the active bridge chiplet, which would be required to access memory channels on individual GPU chiplets. Furthermore, instead of relying on individual chiplet caches, the whole active bridge cache would act similarly to a monolithic GPU cache – the memory would be addressable as a single registry, which would ensure that from software developers’ perspective no chiplet-specific considerations are required.
VideoCardz discusses the features and implications over here. The site notes using chiplets for traditional graphics rendering is a complex task. It's unknown whether the design described in the patents will be used for RDNA architecture first, or whether it will make its introduction in the server market first with CDNA-based products. We do know the industry is moving to chiplets for the datacenter market. Not only AMD but also Intel and NVIDIA are taking this approach.

About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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